Gengjie Chen (陈耿杰)
Ph.D.
Department of Computer Science and Engineering
The Chinese University of Hong Kong
Email: chen_gengjie AT hotmail.com
Biography
I obtained my Ph.D. from the Department of Computer Science and Engineering of The Chinese University of Hong Kong (CUHK) in 2019. My advisor was Prof. Evangeline F. Y. Young. Before that, I received my bachelor degree in the Department of Electronic and Communication Engineering from Sun Yat-sen University (SYSU) in 2015.
My research interests include electronic design automation (EDA), combinatorial optimization, numerical optimization, and machine learning.
Honors
ASPDAC Best Paper Award in 2021 (2 out of 327 submissions) [ASPDAC News] [CUHK-CSE News]
ACM Outstanding Ph.D. Dissertation Award in EDA in 2020 [DAC News]
First Place at ACM Student Research Competition Grand Finals in 2019 [ACM News] [CUHK News] [CUHK-CSE News]
First Place at ACM SIGDA Student Research Competition in 2018 [ACM News] [CUHK-CSE News]
ICCAD Best Paper Award in 2017 (2 out of 399 submissions) [ICCAD News] [CUHK-CSE News]
Hong Kong Ph.D. Fellowship from 2015 to 2019
SYSU Excellent Graduate in 2015
National Scholarship in 2014
SYSU David Sin Excellent Undergraduate Overseas Study Scholarship in 2014
Contest Awards
Second Place at ISPD 2020 Contest on “Wafer-Scale Deep Learning Accelerator Placement”
First Place at ISPD 2019 Contest on “Initial Detailed Routing”
First Place at ICCAD 2018 Contest on “Obstacle-Aware On-Track Bus Routing”
Second Place at ISPD 2018 Contest on “Initial Detailed Routing”
Third Place at ISPD 2017 Contest on “Clock-Aware FPGA Placement”
First Place at ICCAD 2016 Contest on “Non-Exact Projective NPNP Boolean Matching”
Second Place at ISPD 2016 Contest on “Routability-Driven FPGA Placement”
First Place at ICCAD 2015 Contest on “3D Interlayer Cooling Optimized Network”
Publications
Journal Papers
[J5] Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha and Wei Zhang, “AMF-Placer 2.0: Open Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
[J4] Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young and Bei Yu, “Pin-Accessible Legalization for Mixed-Cell-Height Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol 41, no. 1, pp. 143-154, 2022. [Paper]
[J3] Gengjie Chen, Chak-Wa Pui, Haocheng Li and Evangeline F. Y. Young, “Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 9, pp. 1902–1915, 2020. [Paper]
[J2] Gengjie Chen and Evangeline F. Y. Young, “SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 6, pp. 1217–1230, 2020. [Paper]
[J1] Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young and Bei Yu, “RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 10, pp. 2022–2035, 2018. [Paper]
Conference Papers
[C17] Zhongdong Qi, Jingchong Zhang, Gengjie Chen, Hailong You, “Effective and Efficient Detailed Routing with Adaptive Rip-up Scheme and Pin Access Refinement”, ACM Great Lakes Symposium on VLSI (GLSVLSI), Irvine, CA, USA, June 6-8, 2022. [Paper]
[C16] Jinwei Liu, Gengjie Chen and Evangeline F. Y. Young, “REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning”, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, Dec 5-9, 2021. [Paper]
[C15] Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha and Wei Zhang, “AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Munich, Germany, Nov 1-4, 2021. [Paper]
[C14] Wei Li, Yuxiao Qu, Gengjie Chen, Yuzhe Ma and Bei Yu, “TreeNet: Deep Point Cloud Embedding for Routing Tree Construction”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Jan 18-21, 2021. (Best Paper Award) [Paper]
[C13] Benzheng Li, Qi Du, Dingcheng Liu, Jingchong Zhang, Gengjie Chen and Hailong You, “Placement for Wafer-Scale Deep Learning Accelerator”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Jan 18-21, 2021. [Paper]
[C12] Haocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen and Evangeline F. Y. Young, “Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, USA, Nov 4-7, 2019. [Paper] [Slides]
[C11] Jingsong Chen, Jinwei Liu, Gengjie Chen, Dan Zheng and Evangeline F. Y. Young, “MARCH: Maze Routing Under a Concurrent and Hierarchical Scheme for Buses”, ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, USA, June 2–6, 2019. [Paper] [Slides] [Poster]
[C10] Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F. Y. Young and Bei Yu, “FIT: Fill Insertion Considering Timing”, ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, USA, June 2–6, 2019. [Paper] [Slides] [Poster]
[C9] Gengjie Chen and Evangeline F. Y. Young, “Dim Sum: Light Clock Tree by Small Diameter Sum”, IEEE/ACM Design, Automation and Test in Europe (DATE), Florence, Italy, Mar 25-29, 2019. [Paper] [Slides]
[C8] Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang and Evangeline F. Y. Young, “Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan 21-24, 2019. [Paper] [Slides]
[C7] Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young and Bei Yu, “Routability-Driven and Fence-Aware Legalization for Mixed-Cell-Height Circuits”, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, June 24–28, 2018. [Paper] [Slides] [Poster]
[C6] Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen and Evangeline F. Y. Young, “A Two-Step Search Engine for Large Scale Boolean Matching Under NP3 Equivalence”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Jeju Island, Korea, Jan 22-25, 2018. [Paper]
[C5] Gengjie Chen, Peishan Tu and Evangeline F. Y. Young, “SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Irvine, CA, USA, Nov 13-16, 2017. (Best Paper Award) [Paper] [Slides]
[C4] Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young and Bei Yu, “Clock-Aware UltraScale FPGA Placement with Machine Learning Routability Prediction”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Irvine, CA, USA, Nov 13-16, 2017. [Paper] [Slides]
[C3] Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young and Bei Yu, “Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design”, ACM/IEEE Design Automation Conference (DAC), Austin, TX, USA, June 18–22, 2017. [Paper] [Slides] [Poster]
[C2] Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Peishan Tu, Hang Zhang, Evangeline F. Y. Young and Bei Yu, “RippleFPGA: A Routability-Driven Placement for Large-Scale Heterogeneous FPGAs”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, USA, Nov 7-10, 2016. [Paper] [Slides]
[C1] Gengjie Chen, Pierre-Luc St-Charles, Wassim Bouachir, Guillaume-Alexandre Bilodeau and Robert Bergevin, “Reproducible Evaluation of Pan-Tilt-Zoom Tracking”, IEEE International Conference on Image Processing (ICIP), Quebec City, QC, Canada, Sep 27-30, 2015. [Paper] [Slides] [Detailed arXiv version]
Miscellaneous
“VLSI Routing: Seeing Nano Tree in Giga Forest”, ACM Student Research Competition Grand Finals, 2019. (First Place) [Paper]
“VLSI Routing: Seeing Nano Tree in Giga Forest”, Ph.D. Thesis, 2019. (ACM SIGDA Outstanding Ph.D. Dissertation Award) [Thesis]
Tools
REST [C16]
AMP-Placer [J5][C15]
Dr. CU [J3][C12][C8] (Evaluator of ICCAD 2019 Global Routing Contest)
SALT [J2][C5]
RippleFPGA [J1][C4][C2]
VirtualPTZ [C1]
Experiences
Principal Algorithm Engineer | Huawei
On some interesting projects
Oct 2020 - now, Shenzhen, China
Principal Software Engineer | Giga Design Automation
On placement and routing for advanced technology node enablement
Aug 2019 - Oct 2020, Shenzhen, China
Software Engineer Intern | Cadence
On register clustering for high-performance multi-tap clock
Mentored by Zhuo Li and Chuck Alpert
May - Sep 2017, Austin, TX, USA
Software Engineer Intern | Synopsys
On buffer characterization for clock tree synthesis
Mentored by Mike Bezman
June - Sep 2016, Mountain View, CA, USA
Research Intern | Université de Montréal (Polytechnique Montréal)
On reproducible evaluation of pan-tilt-zoom tracking
Supervised by Guillaume-Alexandre Bilodeau
Funded by Canada's MITACS and China Scholarship Council
June - Aug 2014, Montreal, QC, Canada
Teaching
CENG5270 EDA for Physical Design of Digital Systems (2018 Spring)
CSCI2510 Computer Organization (2017 Fall & 2015 Fall)
CENG2010 Digital Logic Design Laboratory (2017 Spring)
CSCI2100 Data Structures (2016 Fall)
CSCI2520 Data Structures and Applications (2016 Spring)